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Philip Brisk, Ajay K. Verma, Paolo Ienne. An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(7):1096-1109, 2010. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Optimal register sharing for high-level synthesis of SSA form programsPhilip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh. tcad, 25(5):772-779, 2006. [doi] Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP designPhilip Brisk, Ajay K. Verma, Paolo Ienne. iccad 2007: 172-179 [doi]
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