Built-in jitter measurement circuit for PLL based on variable vernier delay line

Zhikuang Cai, Haobo Xu, Shanwen Hu, Jun Yang. Built-in jitter measurement circuit for PLL based on variable vernier delay line. IEICE Electronic Express, 14(3):20161116, 2017. [doi]

@article{CaiXHY17,
  title = {Built-in jitter measurement circuit for PLL based on variable vernier delay line},
  author = {Zhikuang Cai and Haobo Xu and Shanwen Hu and Jun Yang},
  year = {2017},
  doi = {10.1587/elex.13.20161116},
  url = {http://dx.doi.org/10.1587/elex.13.20161116},
  researchr = {https://researchr.org/publication/CaiXHY17},
  cites = {0},
  citedby = {0},
  journal = {IEICE Electronic Express},
  volume = {14},
  number = {3},
  pages = {20161116},
}