Ramon Canal, Yiannakis Sazeides, Arkady Bramnik. SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021. pages 711-716, IEEE, 2021. [doi]
@inproceedings{CanalSB21,
title = {SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays},
author = {Ramon Canal and Yiannakis Sazeides and Arkady Bramnik},
year = {2021},
doi = {10.23919/DATE51398.2021.9473986},
url = {https://doi.org/10.23919/DATE51398.2021.9473986},
researchr = {https://researchr.org/publication/CanalSB21},
cites = {0},
citedby = {0},
pages = {711-716},
booktitle = {Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021},
publisher = {IEEE},
isbn = {978-3-9819263-5-4},
}