Ke Cao, Jiang Hu, Mosong Cheng. Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. VLSI Syst., 15(12):1332-1340, 2007. [doi]
@article{CaoHC07,
title = {Wire Sizing and Spacing for Lithographic Printability and Timing Optimization},
author = {Ke Cao and Jiang Hu and Mosong Cheng},
year = {2007},
doi = {10.1109/TVLSI.2007.909807},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2007.909807},
tags = {optimization},
researchr = {https://researchr.org/publication/CaoHC07},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {15},
number = {12},
pages = {1332-1340},
}