A 14-bit 250MS/s digital to analog converter with binary weighted Redundant Signed Digit coding

Benoit Catteau, Bart De Vuyst, Pieter Rombouts, Ludo Weyten. A 14-bit 250MS/s digital to analog converter with binary weighted Redundant Signed Digit coding. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 3345-3348, IEEE, 2010. [doi]

Abstract

Abstract is missing.