Víctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez. Circuit performance optimization for local intra-die process variations using a gate selection metric. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015. pages 165-170, IEEE, 2015. [doi]
@inproceedings{ChampacRG15,
title = {Circuit performance optimization for local intra-die process variations using a gate selection metric},
author = {Víctor H. Champac and Alejandra Nicte-ha Reyes and Andres F. Gomez},
year = {2015},
doi = {10.1109/VLSI-SoC.2015.7314410},
url = {http://dx.doi.org/10.1109/VLSI-SoC.2015.7314410},
researchr = {https://researchr.org/publication/ChampacRG15},
cites = {0},
citedby = {0},
pages = {165-170},
booktitle = {2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
publisher = {IEEE},
isbn = {978-1-4673-9140-5},
}