A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders

Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee. A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. on Circuits and Systems, 56-I(9):1960-1967, 2009. [doi]

Authors

Hsie-Chia Chang

This author has not been identified. Look up 'Hsie-Chia Chang' in Google

Chien-Ching Lin

This author has not been identified. Look up 'Chien-Ching Lin' in Google

Fu-Ke Chang

This author has not been identified. Look up 'Fu-Ke Chang' in Google

Chen-Yi Lee

This author has not been identified. Look up 'Chen-Yi Lee' in Google