Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee. A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. on Circuits and Systems, 56-I(9):1960-1967, 2009. [doi]
@article{ChangLCL09,
title = {A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders},
author = {Hsie-Chia Chang and Chien-Ching Lin and Fu-Ke Chang and Chen-Yi Lee},
year = {2009},
doi = {10.1109/TCSI.2008.2010143},
url = {http://dx.doi.org/10.1109/TCSI.2008.2010143},
researchr = {https://researchr.org/publication/ChangLCL09},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {56-I},
number = {9},
pages = {1960-1967},
}