Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay. A strategy for fault tolerant reconfigurable Network-on-Chip design. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-2, IEEE, 2016. [doi]
@inproceedings{ChatterjeeMC16,
title = {A strategy for fault tolerant reconfigurable Network-on-Chip design},
author = {Navonil Chatterjee and Priyajit Mukherjee and Santanu Chattopadhyay},
year = {2016},
doi = {10.1109/ISVDAT.2016.8064893},
url = {https://doi.org/10.1109/ISVDAT.2016.8064893},
researchr = {https://researchr.org/publication/ChatterjeeMC16},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016},
publisher = {IEEE},
isbn = {978-1-5090-1422-4},
}