A low-power dual-rail inputs write method for bit-interleaved memory cells

Junchao Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang. A low-power dual-rail inputs write method for bit-interleaved memory cells. In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil. pages 325-328, IEEE, 2011. [doi]

Authors

Junchao Chen

This author has not been identified. Look up 'Junchao Chen' in Google

Kwen-Siong Chong

This author has not been identified. Look up 'Kwen-Siong Chong' in Google

Bah-Hwee Gwee

This author has not been identified. Look up 'Bah-Hwee Gwee' in Google

Joseph Sylvester Chang

This author has not been identified. Look up 'Joseph Sylvester Chang' in Google