The following publications are possibly variants of this publication:
- Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data CommunicationsMiao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang. iwsoc 2005: 500-502 [doi]
- A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane ApplicationsMiao Li, Tad A. Kwasniewski, Shoujun Wang. apccas 2006: 1039-1042 [doi]
- FIR filter optimization using bit-edge equalization in high-speed backplane data transmissionLei Zhang, Tadeusz Kwasniewski. mj, 40(10):1449-1457, 2009. [doi]
- A 0.18µm CMOS transceiver design for high-speed backplane data communicationsMiao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang. iscas 2005: 1158-1161 [doi]