A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design

Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu. A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. IEEE Trans. VLSI Syst., 26(10):2118-2131, 2018. [doi]

Authors

Zhengyu Chen

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Huanyu Wang

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Geng Xie

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Jie Gu

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