Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu. A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. IEEE Trans. VLSI Syst., 26(10):2118-2131, 2018. [doi]
@article{ChenWXG18,
title = {A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design},
author = {Zhengyu Chen and Huanyu Wang and Geng Xie and Jie Gu},
year = {2018},
doi = {10.1109/TVLSI.2018.2847622},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2847622},
researchr = {https://researchr.org/publication/ChenWXG18},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {26},
number = {10},
pages = {2118-2131},
}