The following publications are possibly variants of this publication:
- Partitioning Techniques for Built-In Self-Test DesignChien-In Henry Chen. vlsi, 2(3):185-198, 1994. [doi]
- Concurrent Test Scheduling in Built-In Self-Test EnvironmentChien-In Henry Chen, Joel T. Yuen. iccd 1992: 256-259
- Graph Partitioning for Concurrent Test Scheduling in VLSI CircuitChien-In Henry Chen. dac 1991: 287-290 [doi]
- Logic partitioning to pseudo-exhaustive test for BIST designChien-In Henry Chen, Joel T. Yuen. iccad 1993: 646-649 [doi]
- The Partitioning Methodology in Hardware/Software Co-Design Using Extreme Programming: Evaluation through the Lego Robot ProjectHeeseo Chae, Dong-hyun Lee, Jiyong Park, Hoh Peter In. IEEEcit 2006: 187 [doi]
- BISTSYN - A Built-In Self-Test SynthesizerChien-In Henry Chen. iccad 1991: 240-243
- The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving PartitioningHun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen. ieicet, 88-C(5):1061-1069, 2005. [doi]