Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Mai Y. Ching, Ang T. Boon, Chin K. Yeong, Fakhrul Zaman Rokhani. Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1143-1146, IEEE, 2010. [doi]

This author has not been identified. Look up 'Mai Y. Ching' in GoogleThis author has not been identified. Look up 'Ang T. Boon' in GoogleThis author has not been identified. Look up 'Chin K. Yeong' in GoogleThis author has not been identified. Look up 'Fakhrul Zaman Rokhani' in Google

runs on WebDSL