Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus

Mai Y. Ching, Ang T. Boon, Chin K. Yeong, Fakhrul Zaman Rokhani. Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1143-1146, IEEE, 2010. [doi]

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