Mai Y. Ching, Ang T. Boon, Chin K. Yeong, Fakhrul Zaman Rokhani. Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1143-1146, IEEE, 2010. [doi]
@inproceedings{ChingBYR10,
title = {Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus},
author = {Mai Y. Ching and Ang T. Boon and Chin K. Yeong and Fakhrul Zaman Rokhani},
year = {2010},
doi = {10.1109/APCCAS.2010.5775086},
url = {http://dx.doi.org/10.1109/APCCAS.2010.5775086},
researchr = {https://researchr.org/publication/ChingBYR10},
cites = {0},
citedby = {0},
pages = {1143-1146},
booktitle = {2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010},
publisher = {IEEE},
isbn = {978-1-4244-7454-7},
}