Kunhee Cho, Ranjit Gharpurey. A 40-170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS. J. Solid-State Circuits, 51(11):2639-2650, 2016. [doi]
@article{ChoG16a, title = {A 40-170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS}, author = {Kunhee Cho and Ranjit Gharpurey}, year = {2016}, doi = {10.1109/JSSC.2016.2601600}, url = {http://dx.doi.org/10.1109/JSSC.2016.2601600}, researchr = {https://researchr.org/publication/ChoG16a}, cites = {0}, citedby = {0}, journal = {J. Solid-State Circuits}, volume = {51}, number = {11}, pages = {2639-2650}, }