The following publications are possibly variants of this publication:
- A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage VariationsHyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim. jssc, 57(2):562-572, 2022. [doi]
- A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory InterfacesHyunkyu Park, Yong-Un Jeong, Suhwan Kim. access, 10:91888-91896, 2022. [doi]
- A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory InterfacesYong-Un Jeong, Hyunkyu Park, Changho Hyun, Suhwan Kim. vlsic 2020: 1-2 [doi]
- A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory InterfaceYong-Un Jeong, Hyunkyu Park, Changho Hyun, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim. jssc, 56(4):1278-1287, 2021. [doi]
- 22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss MonitorPo-Wei Chiu, Chris H. Kim. isscc 2020: 336-338 [doi]
- A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS TechnologyTaeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae Kang Jung, Jaeduk Han. tcasII, 71(3):1012-1016, March 2024. [doi]
- A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity CompensationKahyun Kim, Daeho Yun, Kyungmin Baek, Woo-seok Choi, Deog Kyoon Jeong. iscas 2023: 1-5 [doi]