Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology - researchr publication related

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T. Cilento, M. Schenkel, C. Yun, R. Mishra, Junjun Li, Kiran V. Chatty, Robert Gauthier. Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology. Microelectronics Reliability, 50(9-11):1367-1372, 2010. [doi]

The following publications are possibly variants of this publication:

A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior ModelsFeilong Zhang, Chenkun Wang, Fei Lu 0004, Qi Chen, Cheng Li, X. Shawn Wang, Daguang Li, Albert Z. Wang. tcad, 38(3):489-498, 2019. [doi]

Compact modeling of on-chip ESD protection devices using Verilog-AJunjun Li, S. Joshi, R. Barnes, E. Rosenbaum. tcad, 25(6):1047-1063, 2006. [doi]

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