Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester. 8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. pages 1-3, IEEE, 2015. [doi]
@inproceedings{ClercSACDBBVZCS15,
title = {8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing},
author = {Sylvain Clerc and Mehdi Saligane and Fady Abouzeid and Martin Cochet and Jean-Marc Daveau and Cyril Bottoni and David Bol and Julien De Vos and Dominique Zamora and Benjamin Coeffic and Dimitri Soussan and Damien Croain and Mehdi Naceur and Pierre Schamberger and Philippe Roche and Dennis Sylvester},
year = {2015},
doi = {10.1109/ISSCC.2015.7062970},
url = {http://dx.doi.org/10.1109/ISSCC.2015.7062970},
researchr = {https://researchr.org/publication/ClercSACDBBVZCS15},
cites = {0},
citedby = {0},
pages = {1-3},
booktitle = {2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015},
publisher = {IEEE},
isbn = {978-1-4799-6224-2},
}