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James Coole, Greg Stitt. Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. Int. J. Reconfig. Comp., 2010, 2010. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body SimulationJames Coole, John Wernsing, Greg Stitt. reconfig 2009: 143-148 [doi] Traversal caches: a first step towards FPGA acceleration of pointer-based data structuresGreg Stitt, Gaurav Chaudhari, James Coole. codes 2008: 61-66 [doi]
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