A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA

Zhiqiang Cui, Zhongfeng Wang. A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Authors

Zhiqiang Cui

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Zhongfeng Wang

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