Zhiqiang Cui, Zhongfeng Wang. A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]
@inproceedings{CuiW06:0,
title = {A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA},
author = {Zhiqiang Cui and Zhongfeng Wang},
year = {2006},
doi = {10.1109/ISCAS.2006.1693778},
url = {http://dx.doi.org/10.1109/ISCAS.2006.1693778},
researchr = {https://researchr.org/publication/CuiW06%3A0},
cites = {0},
citedby = {0},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece},
publisher = {IEEE},
}