Efficient post-layout timing verification via RLC trees and explicit PWL timing integration - researchr publication

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Jerzy J. Dabrowski. Efficient post-layout timing verification via RLC trees and explicit PWL timing integration. In Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002. pages 689-692, IEEE, 2002. [doi]

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