Jerzy J. Dabrowski - researchr alias

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Viewing Publication 1 - 10 from 10

2020

One-Bit ΣΔ-Encoded Stimulus Generation for On-Chip ADC TestShakeel Ahmad, Jerzy J. Dabrowski. jcsc, 29(15), 2020. [doi]

2019

Design of Two-Tone RF Generator for On-Chip IP3/IP2 TestShakeel Ahmad, Jerzy J. Dabrowski. et, 35(1):77-85, 2019. [doi]

2016

Tunable selective receiver front end with impedance transformation filteringFahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski. ijcta, 44(5):1071-1093, 2016. [doi]

2015

Passive SC Sigma Delta Modulators Revisited: Analysis and Design StudyFahad Qazi, Jerzy J. Dabrowski. esticas, 5(4):624-637, 2015. [doi]

2009

On-chip stimuli generation for ADC dynamic test by ΣΔ techniqueShakeel Ahmad, Jerzy J. Dabrowski. ecctd 2009: 105-108 [doi]

2007

Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOSStefan Back Andersson, Rashad Ramzan, Jerzy J. Dabrowski, Christer Svensson. ecctd 2007: 168-171 [doi]

2005

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOSDarius Jakonis, Kalle Folkesson, Jerzy J. Dabrowski, Patrik Eriksson, Christer Svensson. jssc, 40(6):1265-1277, 2005. [doi]

2003

Lookback BiST for RF front-ends in digital transceiversJerzy J. Dabrowski. issoc 2003: 143-146 [doi]

2002

Efficient post-layout timing verification via RLC trees and explicit PWL timing integrationJerzy J. Dabrowski. icecsys 2002: 689-692 [doi]

1992

Efficient timing verification via mixed-mode techniqueJerzy J. Dabrowski. jsa, 34(1-5):183-186, 1992. [doi]

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