Abstract is missing.
- SOC logic development using configurable, application-specific processorsChris Rowen, Steve Leibson. [doi]
- Moustique: smaller than an ASIC and fully programmableBernardo Kastrup, Antoine van Wel. [doi]
- CTL based DFT solution to accelerate design to test development for system on chip devicesSalvatore Talluto. [doi]
- A programmable platform for software-defined radioHans-Martin Blüthgen, Cyprian Grassmann, Wolfgang Raab, Ulrich Ramacher. [doi]
- SoC integration of programmable coresAndreas Hoffmann, Richard Langridge, Dave Machin. [doi]
- Accelerating system performance using SOPC builderBrian Dalay. 3-5 [doi]
- Performance of dynamically scheduling VLIW instructionsSunghyun Jee, Kannappan Palaniappan. 7-10 [doi]
- COFFEE - a core for freeJuha Kylliäinen, Jari Nurmi, Mika Kuulusa. 17-22 [doi]
- One-chip solution in 0.35 μm standard CMOS for electronic ballasts for fluorescent lampsDirk Killat, Joachim Schmidt, Andreas Baumgaertner, Robert Baraniecki, Oliver Salzmann. 23-26 [doi]
- Evaluating application mapping using network simulationTommi Salminen, Juha-Pekka Soininen. 27-30 [doi]
- A guaranteed-throughput switch for network-on-chipJian Liu, Li-Rong Zheng, Hannu Tenhunen. 31-34 [doi]
- A code compression scheme for improving SoC performanceE. G. Nikolova, David J. Mulvaney, Vassilios A. Chouliaras, José L. Núñez-Yáñez. 35-40 [doi]
- AMBA based multiprocessor systemYoungWoo Kim, Kyoung Park, Myungjoon Kim. 41-42 [doi]
- Updating matrix inverse in fixed-point representation: direct versus iterative methodsMikko Ylinen, Adrian Burian, Jarmo Takala. 45-48 [doi]
- SoC platform architecture for a network processorHany Ghattas, M. Mbaye, J. Pepga Bissou, Yvon Savaria. 49-52 [doi]
- A low power datapath for algebraic codebook search targeting a generic GSM system-on-chip platformTony Kirkham, Tughrul Arslan, Fred Westall, David H. Crawford. 53-56 [doi]
- Complexity analysis of spatially scalable MPEG-4 encoderOlli Lehtoranta, Timo D. Hämäläinen. 57-60 [doi]
- Implementing user and application specific algorithms within IP-methodology: a coarse-grain-approachTapio Ristimäki, J. Nurmi. 61-64 [doi]
- Immediate optimization for compressed transport triggered architecture instructionsJari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal. 65-68 [doi]
- A C-based algorithm development flow for a reconfigurable processor architectureClaudio Mucci, Carlo Chiesa, Andrea Lodi 0002, Mario Toma, Fabio Campi. 69-73 [doi]
- xICU - in interrupt control unit for a configurable DSP coreChristian Panis, J. Hohl, Herbert Grünbacher, Jari Nurmi. 75-78 [doi]
- Highly scalable network on chip for reconfigurable systemsT. Andrei Bartic, Jean-Yves Mignolet, Vincent Nollet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins. 79-82 [doi]
- A highly efficient modeling style for heterogeneous bus architecturesManoj Ariyamparambath, Denis Bussaglia, Bernd Reinkemeier, Tim Kogel, Torsten Kempf. 83-87 [doi]
- Modeling on-chip communicationTiberiu Seceleanu, Juha Plosila. 89-92 [doi]
- Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellationIlhan Hatirnaz, Yusuf Leblebici. 93-96 [doi]
- Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC busesKanak Agarwal, Dennis Sylvester, David T. Blaauw. 97-100 [doi]
- A driver load model for capacitive coupled on-chip interconnect busesMarkus Tahedl, Hans-Jörg Pfleiderer. 101-104 [doi]
- Using a communication generator in SoC architecture explorationTero Kangas, Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen. 105-108 [doi]
- Arithmetic processing unit for reciprocal operationsKim Rounioja, Jari A. Parviainen. 109-112 [doi]
- New adaptive routing algorithm for extended generalized fat trees on-chipHeikki Kariniemi, Jari Nurmi. 113-118 [doi]
- Mappability estimate: a measure of the goodness of a processor-algorithm pairJari Kreku, Juha-Pekka Soininen. 119-122 [doi]
- Multiple-objective backtrace for solving test generation constraintsAndrei Mekler, Jaan Raik. 123-126 [doi]
- A system level IP integration methodology for fast SOC designMassimo Bocchi, Claudio Brunelli, Claudia De Bartolomeis, Luca Magagni, Fabio Campi. 127-130 [doi]
- VLIW operation refinement for reducing energy consumptionUlrich Hirnschrott, Andreas Krall. 131-134 [doi]
- A delay spread based low power reconfigurable FFT processor architecture for wireless receiverMohd. Hasan, Tughrul Arslan, John S. Thompson. 135-138 [doi]
- Design of a parametrizable low cost Ethernet MAC core for SoC solutionsJosé Antonio Moreno Zamora, Pedro José Rodriguez Corrales, Juan Manuel Sánchez-Pérez. 139-142 [doi]
- Lookback BiST for RF front-ends in digital transceiversJerzy J. Dabrowski. 143-146 [doi]
- Abstract RTOS modeling for multiprocessor system-on-chipJan Madsen, Kashif Virk, Mercury Gonzales. 147-150 [doi]
- th integrated circuitsRobert Bai, Dennis Sylvester. 151-154 [doi]
- Evaluation of fully-integrated switching regulators for CMOS process technologiesJaeseo Lee, Geoff Hatcher, Lieven Vandenberghe, Chih-Kong Ken Yang. 155-158 [doi]
- Mixed static/dynamic profiling for dictionary based code compressionEduardo Braulio Wanderley Netto, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo. 159-163 [doi]
- AVISPA: a massively parallel reconfigurable acceleratorJeroen A. J. Leijten, Geoffrey Burns, Jos Huisken, Erwin Waterlander, Antoine van Wel. 165-168 [doi]