An improved output compaction technique for built-in self-test in VLSI circuits

Sunil R. Das, H. T. Ho, Wen-Ben Jone, A. R. Nayak. An improved output compaction technique for built-in self-test in VLSI circuits. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 403-407, IEEE Computer Society, 1995. [doi]

Authors

Sunil R. Das

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H. T. Ho

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Wen-Ben Jone

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A. R. Nayak

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