Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer - researchr publication authors

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Takahiro Deguchi, Tetsushi Koide, Shin ichi Wakabayashi. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 99-104, ACM, 2000. [doi]

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