Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

Takahiro Deguchi, Tetsushi Koide, Shin ichi Wakabayashi. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 99-104, ACM, 2000. [doi]

@inproceedings{DeguchiKW00,
  title = {Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer},
  author = {Takahiro Deguchi and Tetsushi Koide and Shin ichi Wakabayashi},
  year = {2000},
  doi = {10.1145/368434.368586},
  url = {http://doi.acm.org/10.1145/368434.368586},
  tags = {routing},
  researchr = {https://researchr.org/publication/DeguchiKW00},
  cites = {0},
  citedby = {0},
  pages = {99-104},
  booktitle = {Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan},
  publisher = {ACM},
  isbn = {0-7803-5974-7},
}