Abstract is missing.
- Multi-Stack Optimization for Data-Path Chip (Microprocessor) LayoutWing K. Luk, Alvar A. Dean. 110-115 [doi]
- Locating Functional Errors in Logic CircuitsK. A. Tamura. 185-191 [doi]
- Experience with D-BUS Architecture for a Design Automation FrameworkE. C. VanHorn, Roy R. Rezac. 209-214 [doi]
- An Automatic Test Generation Algorithm for Hardware Description LanguagesF. E. Norrod. 429-434 [doi]
- MIOS: A Flexible System for PCB ManufacturingAangelo C. Hung, Philip M. Reddy, Paul J. Hammer. 460-465 [doi]
- MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous CircuitsT. Ogihara, K. Muroi, G. Yonemori, S. Murai. 519-524 [doi]
- ACE: A Hierarchical Graphical Interface for Architectual SynthesisO. A. Buset, Mohamed I. Elmasry. 537-542 [doi]
- Rule-based VLSI Verification System Constrained by Layout ParasiticsJacques Wenin, Johan Verhasselt, Marc Van Camp, Jean Leonard, Pierre Guebels. 662-667 [doi]
- Extracting Schematic-like Information from CMOS Circuit Net-listsW.-J. Lue, Lawrence P. McNamee. 690-693 [doi]
- CrossCheck: A Cell Based VLSI Testability SolutionT. Ghewala. 706-709 [doi]
- Partitioning by Probability CondensationJ. Blanks. 758-761 [doi]
- Optimum Design of Reliable IC Power Networks Having General Graph TopologiesS. Chowdhury. 787-790 [doi]
- CEDIF: A Data Driven EDIF ReaderM. Roberts. 818-821 [doi]