The following publications are possibly variants of this publication:
- A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT CalibrationAhmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. jssc, 49(1):50-60, 2014. [doi]
- A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generationWei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. aspdac 2014: 21-22 [doi]
- An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dBDongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. esscirc 2016: 197-200 [doi]
- A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration techniqueBangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa. cicc 2018: 1-4 [doi]
- 2 3mW synthesizable fractional-N PLL with a soft injection-locking techniqueWei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. isscc 2015: 1-3 [doi]