DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen. DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. In 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012. pages 1-10, IEEE Computer Society, 2012. [doi]

This author has not been identified. Look up 'Sergej Deutsch' in GoogleThis author has not been identified. Look up 'Brion L. Keller' in GoogleThis author has not been identified. Look up 'Vivek Chickermane' in GoogleThis author has not been identified. Look up 'Subhasish Mukherjee' in GoogleThis author has not been identified. Look up 'Navdeep Sood' in GoogleThis author has not been identified. Look up 'Sandeep Kumar Goel' in GoogleThis author has not been identified. Look up 'Ji-Jan Chen' in GoogleThis author has not been identified. Look up 'Ashok Mehta' in GoogleThis author has not been identified. Look up 'Frank Lee' in GoogleThis author has not been identified. Look up 'Erik Jan Marinissen' in Google

runs on WebDSL