Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits

Srinivas Devadas, Kurt Keutzer. Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. In DAC. pages 221-227, 1990. [doi]

Authors

Srinivas Devadas

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Kurt Keutzer

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