A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation - researchr publication references

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Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. J. Solid-State Circuits, 46(11):2500-2513, 2011. [doi]

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