A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. J. Solid-State Circuits, 46(11):2500-2513, 2011. [doi]

Abstract

Abstract is missing.