A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation - researchr publication related

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Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. J. Solid-State Circuits, 46(11):2500-2513, 2011. [doi]

The following publications are possibly variants of this publication:

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline AlignmentBenjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada. ieicet, 93-A(7):1319-1328, 2010. [doi]

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