Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)

T. Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond. Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC). In 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France. pages 157-162, IEEE Computer Society, 2002. [doi]

Authors

T. Devoivre

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M. Lunenborg

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C. Julien

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J.-P. Carrere

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P. Ferreira

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W. J. Toren

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A. VandeGoor

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P. Gayet

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T. Berger

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O. Hinsinger

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P. Vannier

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Y. Trouiller

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Y. Rody

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P.-J. Goirand

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R. Palla

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I. Thomas

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F. Guyader

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D. Roy

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B. Borot

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N. Planes

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S. Naudet

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F. Pico

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D. Duca

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F. Lalanne

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D. Heslinga

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M. Haond

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