Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates) - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu. Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). In 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016. pages 139-146, IEEE, 2016. [doi]

This author has not been identified. Look up 'Yi Diao' in GoogleThis author has not been identified. Look up 'Xing Wei' in GoogleThis author has not been identified. Look up 'Tak-Kei Lam' in GoogleThis author has not been identified. Look up 'Yu-Liang Wu' in Google

runs on WebDSL