Abstract is missing.
- An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injectionDongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. 1-2 [doi]
- Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitterChak-Fong Cheang, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins. 3-4 [doi]
- A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation techniqueAravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa. 5-6 [doi]
- A 2.2µW 15b incremental delta-sigma ADC with output-driven input segmentationBo Wang, Man Kay Law, Saqib Mohamad, Amine Bermak. 7-8 [doi]
- A 200-MHz 4-phase fully integrated voltage regulator with local ground sensing dual loop ZDS hysteretic control using 6.5nH package bondwire inductors on 65nm bulk CMOSMinkyu Song, Joseph Sankman, Jayeol Lee, Dongsheng Brian Ma. 9-10 [doi]
- An AC powered converter-free LED driver with low flickerYuan Gao, Lisong Li, Philip K. T. Mok. 11-12 [doi]
- A variable-voltage low-power technique for digital circuit systemAn-Tia Xiao, Yung-Siang Miao, Ching-Hwa Cheng, Jiun-In Guo. 13-14 [doi]
- Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniquesMingzhong Li, Chio-In Ieong, Man Kay Law, Pui-In Mak, Mang I Vai, Sio-Hang Pun, Rui Paulo Martins. 15-16 [doi]
- A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scalingLiang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin. 17-18 [doi]
- Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standardQing Lu, Chiu-Wing Sham, Francis C. M. Lau. 19-20 [doi]
- Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoringChio-In Ieong, Pui-In Mak, Mang I Vai, Rui Paulo Martins. 21-22 [doi]
- Design of an energy-autonomous, disposable, supply-sensing biosensor using bio fuel cell and 0.23-V 0.25-µm zero-Vth all-digital CMOS supply-controlled ring oscillator with inductive transmitterKiichi Niitsu, Atsuki Kobayashi, Yudai Ogawa, Matsuhiko Nishizawa, Kazuo Nakazato. 23-24 [doi]
- Performance-centric register file design for GPUs using racetrack memoryShuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun, Yongpan Liu, Yu Wang, Xiuhong Li. 25-30 [doi]
- Improving read performance of STT-MRAM based main memories through Smash Read and Flexible ReadLei Jiang, Wujie Wen, Danghui Wang, Lide Duan. 31-36 [doi]
- STLAC: A spatial and temporal locality-aware cache and network-on-chip codesign for tiled many-core systemsMingyu Wang, Zhaolin Li. 37-42 [doi]
- A lightweight OpenMP4 run-time for embedded systemsRoberto Vargas, Sara Royuela, Maria A. Serrano, Xavier Martorell, Eduardo Quiñones. 43-49 [doi]
- Improving tag generation for memory data authentication in embedded processor systemsTao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu. 50-55 [doi]
- JTAG-based robust PCB authentication for protection against counterfeiting attacksAndrew Hennessy, Yu Zheng, Swarup Bhunia. 56-61 [doi]
- Maximizing level of confidence for non-equidistant CheckpointingDimitar Nikolov, Erik Larsson. 62-68 [doi]
- A mutual auditing framework to protect IoT against hardware TrojansChen Liu, Patrick Cronin, Chengmo Yang. 69-74 [doi]
- Simultaneous template optimization and mask assignment for DSA with multiple patterningJian Kuang 0001, Junjie Ye, Evangeline F. Y. Young. 75-82 [doi]
- Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithographySeongbo Shim, Youngsoo Shin. 83-88 [doi]
- Cut redistribution with directed self-assembly templates for advanced 1-D gridded layoutsZhi-Wen Lin, Yao-Wen Chang. 89-94 [doi]
- Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layoutZigang Xiao, Chun-Xun Lin, Martin D. F. Wong, Hongbo Zhang. 95-102 [doi]
- Logic and memory design using spin-based circuitsZhaoxin Liang, Meghna Mankalale, Brandon Del Bel, Sachin S. Sapatnekar. 103-108 [doi]
- Architecture design with STT-RAM: Opportunities and challengesPing Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, Yuan Xie 0001. 109-114 [doi]
- Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapsesAbhronil Sengupta, Karthik Yogendra, Deliang Fan, Kaushik Roy. 115-120 [doi]
- Automatic abstraction refinement of TR for PDRKuan Fan, Ming-Jen Yang, Chung-Yang Huang. 121-126 [doi]
- A complete approach to unreachable state diagnosability via property directed reachabilityRyan Berryhill, Andreas G. Veneris. 127-132 [doi]
- Formally analyzing fault tolerance in datapath designs using equivalence checkingPayman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita. 133-138 [doi]
- Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates)Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu. 139-146 [doi]
- NVPsim: A simulator for architecture explorations of nonvolatile processorsYizi Gu, Yongpan Liu, Yiqun Wang, Hehe Li, Huazhong Yang. 147-152 [doi]
- MCSSim: A memory channel storage simulatorRenhai Chen, Zili Shao, Chia-Lin Yang, Tao Li. 153-158 [doi]
- Trace-based context-sensitive timing simulation considering execution path variationsSebastian Ottlik, Jan Micha Borrmann, Sadik Asbach, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann. 159-165 [doi]
- Generating high coverage tests for SystemC designs using symbolic executionBin Lin, Zhenkun Yang, Kai Cong, Fei Xie. 166-171 [doi]
- Circular-contour-based obstacle-aware macro placementChien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang. 172-177 [doi]
- Learning-based prediction of embedded memory timing failures during initial floorplan designWei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath. 178-185 [doi]
- Stitch aware detailed placement for multiple e-beam lithographyYibo Lin, Bei Yu, Yi Zou, Zhuo Li 0001, Charles J. Alpert, David Z. Pan. 186-191 [doi]
- Minimum implant area-aware placement and threshold voltage refinementSeong-I Lei, Wai-Kei Mak, Chris Chu. 192-197 [doi]
- Design and verification using high-level synthesisAndrés Takach. 198-203 [doi]
- High-level synthesis of accelerators in embedded scalable platformsPaolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni. 204-211 [doi]
- High quality IP design using high-level synthesis design flowQiang Zhu, Masato Tatsuoka. 212-217 [doi]
- Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesisZelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen. 218-225 [doi]
- Clock buffer polarity assignment utilizing useful clock skews for power noise reductionDeokjin Joo, Taewhan Kim. 226-231 [doi]
- Buffer insertion to remove hold violations at multiple process cornersInhak Han, Daijoon Hyun, Youngsoo Shin. 232-237 [doi]
- Speed binning with high-quality structural patterns from functional timing analysis (FTA)Louis Y.-Z. Lin, Charles H.-P. Wen. 238-243 [doi]
- Electromigration recovery modeling and analysis under time-dependent current and temperature stressingXin Huang, Valeriy Sukharev, Taeyoung Kim, Hai-Bao Chen, Sheldon X.-D. Tan. 244-249 [doi]
- A novel low-cost dynamic logic reconfigurable structure strategy for low power optimizationYu-Guang Chen, Wan-yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang. 250-255 [doi]
- An energy-efficient random number generator for stochastic circuitsKyounghoon Kim, Jongeun Lee, Kiyoung Choi. 256-261 [doi]
- Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reductionShang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang. 262-267 [doi]
- Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimizationHyoungseok Moon, Taewhan Kim. 268-273 [doi]
- Thermal optimization for memristor-based hybrid neuromorphic computing systemsChi-Ruo Wu, Wei Wen, Tsung-Yi Ho, Yiran Chen. 274-279 [doi]
- An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbarLeibin Ni, Yuhao Wang, Hao Yu, Wei Yang, Chuliang Weng, Junfeng Zhao. 280-285 [doi]
- A racetrack memory based in-memory booth multiplier for cryptography applicationTao Luo, Wei Zhang, Bingsheng He, Douglas L. Maskell. 286-291 [doi]
- Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuitsRobert Wille, Oliver Keszocze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler. 292-297 [doi]
- Energy-efficient system design for IoT devicesHrishikesh Jayakumar, Arnab Raha, Younghyun Kim, Soubhagya Sutar, Woo Suk Lee, Vijay Raghunathan. 298-301 [doi]
- (Invited paper) energy delivery for self-powered IoT devicesKhondker Z. Ahmed, Monodeep Kar, Saibal Mukhopadhyay. 302-307 [doi]
- Efficient embedded learning for IoT devicesSwagath Venkataramani, Kaushik Roy, Anand Raghunathan. 308-311 [doi]
- Computing with coupled Spin Torque Nano OscillatorsKarthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy. 312-317 [doi]
- ApproxMap: On task allocation and scheduling for resilient applicationsJuan Yi, Qian Zhang, Ye Tian, Ting Wang, Weichen Liu, Edwin Hsing-Mean Sha, Qiang Xu. 318-323 [doi]
- Energy optimization of stochastic applications with statistical guarantees of deadline and reliabilityXiong Pan, Wei Jiang, Ke Jiang, Liang Wen, Qi Dong. 324-329 [doi]
- SMoSi: A framework for the derivation of sleep mode traces from RTL simulationsDustin Peterson, Oliver Bringmann. 330-335 [doi]
- Optimization of behavioral IPs in multi-processor system-on-chipsYidi Liu, Benjamin Carrión Schäfer. 336-341 [doi]
- A novel PUF based on cell error rate distribution of STT-RAMXian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di. 342-347 [doi]
- Data privacy in non-volatile cache: Challenges, attack models and solutionsNitin Rathi, Swaroop Ghosh, Anirudh Iyengar, Helia Naeimi. 348-353 [doi]
- Pin Tumbler Lock: A shift based encryption mechanism for racetrack memoryHongbin Zhang, Chao Zhang, Xian Zhang, Guangyu Sun, Jiwu Shu. 354-359 [doi]
- Routing path reuse maximization for efficient NV-FPGA reconfigurationYuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu. 360-365 [doi]
- MCMM clock tree optimization based on slack redistribution using a reduced slack graphRickard Ewetz, Cheng-Kok Koh. 366-371 [doi]
- Dynamic planning of local congestion from varying-size vias for global routing layer assignmentDaohang Shi, Edward Tashjian, Azadeh Davoodi. 372-377 [doi]
- Negotiation-based track assignment considering local netsMan-Pan Wong, Wen-Hao Liu, Ting-Chi Wang. 378-383 [doi]
- Ordered Escape routing for grid pin array based on Min-cost Multi-commodity FlowFengxian Jiao, Sheqin Dong. 384-389 [doi]
- Efficient reliability management in SoCs - an approximate DRAM perspectiveMatthias Jung 0001, Deepak M. Mathew, Christian Weis, Norbert Wehn. 390-394 [doi]
- Cross-layer virtual/physical sensing and actuation for resilient heterogeneous many-core SoCsSantanu Sarma, Tiago Muck, Majid Shoushtari, Abbas BanaiyanMofrad, Nikil Dutt. 395-402 [doi]
- On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operationsIslam A. K. M. Mahfuzul, Hidetoshi Onodera. 403-409 [doi]
- Embedded software reliability testing by unit-level fault injectionPetra R. Maier, Veit B. Kleeberger. 410-416 [doi]
- Thermal modeling for energy-efficient smart building with advanced overfitting mitigation techniqueWandi Liu, Hai Wang, Hengyang Zhao, Shujuan Wang, Hai-Bao Chen, Yuzhuo Fu, Jian Ma, Xin Li, Sheldon X.-D. Tan. 417-422 [doi]
- Modeling, analysis, and optimization of Electric Vehicle HVAC systemsMohammad Abdullah Al Faruque, Korosh Vatanparvar. 423-428 [doi]
- Distributed reconfigurable Battery System Management ArchitecturesSebastian Steinhorst, Zili Shao, Samarjit Chakraborty, Matthias Kauer, Shuai Li, Martin Lukasiewycz, Swaminathan Narayanaswamy, Muhammad Usman Rafique, Qixin Wang. 429-434 [doi]
- Minimum-energy driving speed profiles for low-speed electric vehiclesDonkyu Baek, Joonki Hong, Naehyuck Chang. 435 [doi]
- Multi-version checkpointing for flash file systemsShih-Chun Chou, Yuan-Hao Chang, Yuan-Hung Kuan, Po-Chun Huang, Che-Wei Tsao. 436-443 [doi]
- Relay-based key management to support secure deletion for resource-constrained flash-memory storage devicesWei-Lin Wang, Yuan-Hao Chang, Po-Chun Huang, Chia-Heng Tu, Hsin-Wen Wei, Wei Kuan Shih. 444-449 [doi]
- Peak-to-average pumping efficiency improvement for charge pump in Phase Change MemoriesHuizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, Qingfeng Zhuge. 450-455 [doi]
- Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architecturesXinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei. 456-461 [doi]
- SlowMo - enhancing mobile gesture-based authentication schemes via sampling rate optimizationKent W. Nixon, Xiang Chen, Zhi-Hong Mao, Yiran Chen. 462-467 [doi]
- Lattice-based Boolean diagramsAhmed Nassar, Fadi J. Kurdahi. 468-473 [doi]
- BDD minimization for approximate computingMathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler. 474-479 [doi]
- MajorSat: A SAT solver to majority logicYu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang. 480-485 [doi]
- Fast synthesis of threshold logic networks with optimizationYung-Chih Chen, Runyi Wang, Yan-Ping Chang. 486-491 [doi]
- Polysynchronous stochastic circuitsM. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan. 492-498 [doi]
- Majority-based synthesis for nanotechnologiesLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 499-502 [doi]
- A scalable communication-aware compilation flow for programmable acceleratorsJason Cong, Hui Huang 0001, Mohammad Ali Ghodrat. 503-510 [doi]
- Enabling multi-layer cyber-security assessment of Industrial Control Systems through Hardware-In-The-Loop testbedsAnastasis Keliris, Charalambos Konstantinou, Nektarios Georgios Tsoutsos, Raghad Baiad, Michail Maniatakos. 511-518 [doi]
- Security analysis on consumer and industrial IoT devicesJacob Wurm, Khoa Hoang, Orlando Arias, Ahmad-Reza Sadeghi, Yier Jin. 519-524 [doi]
- Covert channels using mobile device's magnetic field sensorsNikolay Matyunin, Jakub Szefer, Sebastian Biedermann, Stefan Katzenbeisser 0001. 525-532 [doi]
- Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementationSiarhei S. Zalivaka, Alexander V. Puchkov, Vladimir P. Klybik, Alexander A. Ivaniuk, Chip-Hong Chang. 533-538 [doi]
- Every test makes a difference: Compressing analog tests to decrease production costsSeyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan. 539-544 [doi]
- Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexificationFa Wang, Shihui Yin, Minhee Jun, Xin Li 0001, Tamal Mukherjee, Rohit Negi, Larry T. Pileggi. 545-550 [doi]
- An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolationChenjie Yang, Fan Yang, Xuan Zeng, Dian Zhou. 551-556 [doi]
- STORM: A nonlinear model order reduction method via symmetric tensor decompositionJian Deng, Haotian Liu, Kim Batselier, Yu-Kwong Kwok, Ngai Wong. 557-562 [doi]
- Footfall - GPS polling scheduler for power saving on wearable devicesKent W. Nixon, Xiang Chen, Yiran Chen. 563-568 [doi]
- CP-FPGA: Computation data-aware software/hardware co-design for nonvolatile FPGAs based on checkpointing techniquesZhe Yuan, Yongpan Liu, Hehe Li, Huazhong Yang. 569-574 [doi]
- Design space exploration of FPGA-based Deep Convolutional Neural NetworksMohammad Motamedi, Philipp Gysel, Venkatesh Akella, Soheil Ghiasi. 575-580 [doi]
- LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank ApproximationJingyang Zhu, Zhiliang Qian, Chi-Ying Tsui. 581-586 [doi]
- Sequence-pair-based placement and routing for flow-based microfluidic biochipsQin Wang, Yizhong Ru, Hailong Yao, Tsung-Yi Ho, Yici Cai. 587-592 [doi]
- Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochipsJain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho. 593-598 [doi]
- Chain-based pin count minimization for general-purpose digital microfluidic biochipsYung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou. 599-604 [doi]
- A routability-driven flow routing algorithm for programmable microfluidic devicesYi-Siang Su, Tsung-Yi Ho, Der-Tsai Lee. 605-610 [doi]
- Advanced multi-patterning and hybrid lithography techniquesFedor G. Pikus, Andres J. Torres. 611-616 [doi]
- Recent research development and new challenges in analog layout synthesisMark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung. 617-622 [doi]
- To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECOXing Wei, Yi Diao, Yu-Liang Wu. 623-630 [doi]
- Aging-aware high-level physical planning for reconfigurable systemsZana Ghaderi, Eli Bozorgzadeh. 631-636 [doi]
- Hardware Reliability margining for the dark silicon eraLiangzhen Lai, Puneet Gupta. 637-642 [doi]
- ACR: Enabling computation reuse for approximate computingXin He, Guihai Yan, Yinhe Han, Xiaowei Li 0001. 643-648 [doi]
- Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenationXinfei Guo, Mircea R. Stan. 649-654 [doi]
- Netlist reverse engineering for high-level functionality reconstructionTravis Meade, Shaojie Zhang, Yier Jin. 655-660 [doi]
- Assessing CPA resistance of AES with different fault tolerance mechanismsHoda Pahlevanzadeh, Jaya Dofe, Qiaoyan Yu. 661-666 [doi]
- SPARTA: A scheduling policy for thwarting differential power analysis attacksKe Jiang, Petru Eles, Zebo Peng, Sudipta Chattopadhyay 0001, Lejla Batina. 667-672 [doi]
- Laplacian eigenmaps and bayesian clustering based layout pattern sampling and its applications to hotspot detection and OPCTetsuaki Matsunawa, Bei Yu, David Z. Pan. 679-684 [doi]
- Balancing lifetime and soft-error reliability to improve system availabilityJunlong Zhou, Xiaobo Sharon Hu, Yue Ma, Tongquan Wei. 685-690 [doi]
- A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage regionTatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 691-696 [doi]
- Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM productsSamyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo. 697-704 [doi]
- Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuitsUlf Schlichtmann, Masanori Hashimoto, Iris Hui-Ru Jiang, Bing Li. 705-711 [doi]
- A high performance reliable NoC eouterLu Wang, Sheng Ma, Zhiying Wang. 712-718 [doi]
- Dynamic admission control for real-time networks-on-chipsAdam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst. 719-724 [doi]
- FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systemsLei Yang, Weichen Liu, Weiwen Jiang, Mengquan Li, Juan Yi, Edwin Hsing-Mean Sha. 725-730 [doi]
- Analytical thruchip inductive coupling channel design optimizationLi-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda. 731-736 [doi]
- Extending trace history through tapered summaries in post-silicon validationSandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi. 737-742 [doi]
- Novel applications of deep learning hidden features for adaptive testingBingjun Xiao, Jinjun Xiong, Yiyu Shi. 743-748 [doi]
- Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknownsDominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. 749-754 [doi]
- Test and diagnosis pattern generation for dynamic bridging faults and transition delay faultsCheng-Hung Wu, Saint James Lee, Kuen-Jong Lee. 755-760 [doi]
- Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scalingYing-Yu Chen, Morteza Gholipour, Deming Chen. 761-768 [doi]
- Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computingRajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori. 769-774 [doi]
- Optimal co-scheduling of HVAC control and battery management for energy-efficient buildings considering state-of-health degradationTiansong Cui, Shuang Chen, Yanzhi Wang, Qi Zhu, Shahin Nazarian, Massoud Pedram. 775-780 [doi]
- Accurate remaining range estimation for Electric vehiclesJoonki Hong, Sangjun Park, Naehyuck Chang. 781-786 [doi]