Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques

Mingzhong Li, Chio-In Ieong, Man Kay Law, Pui-In Mak, Mang I Vai, Sio-Hang Pun, Rui Paulo Martins. Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. In 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016. pages 15-16, IEEE, 2016. [doi]

Abstract

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