Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu. Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). In 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016. pages 139-146, IEEE, 2016. [doi]
@inproceedings{DiaoWLW16,
title = {Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates)},
author = {Yi Diao and Xing Wei and Tak-Kei Lam and Yu-Liang Wu},
year = {2016},
doi = {10.1109/ASPDAC.2016.7428002},
url = {http://dx.doi.org/10.1109/ASPDAC.2016.7428002},
researchr = {https://researchr.org/publication/DiaoWLW16},
cites = {0},
citedby = {0},
pages = {139-146},
booktitle = {21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, January 25-28, 2016},
publisher = {IEEE},
isbn = {978-1-4673-9569-4},
}