A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems

Qing Dong, Kaiyuan Yang, David Blaauw, Dennis Sylvester. A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems. In 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016. pages 1-2, IEEE, 2016. [doi]

@inproceedings{DongYBS16,
  title = {A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems},
  author = {Qing Dong and Kaiyuan Yang and David Blaauw and Dennis Sylvester},
  year = {2016},
  doi = {10.1109/VLSIC.2016.7573494},
  url = {http://dx.doi.org/10.1109/VLSIC.2016.7573494},
  researchr = {https://researchr.org/publication/DongYBS16},
  cites = {0},
  citedby = {0},
  pages = {1-2},
  booktitle = {2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016},
  publisher = {IEEE},
  isbn = {978-1-5090-0635-9},
}