Testing the Logic Cells and Interconnect Resources for FPGAs

Abderrahim Doumar, Hideo Ito. Testing the Logic Cells and Interconnect Resources for FPGAs. In 8th Asian Test Symposium (ATS 99), 16-18 November 1999, Shanghai, China. pages 369-374, IEEE Computer Society, 1999. [doi]

@inproceedings{DoumarI99,
  title = {Testing the Logic Cells and Interconnect Resources for FPGAs},
  author = {Abderrahim Doumar and Hideo Ito},
  year = {1999},
  url = {http://csdl.computer.org/comp/proceedings/ats/1999/0315/00/03150369abs.htm},
  tags = {testing, logic},
  researchr = {https://researchr.org/publication/DoumarI99},
  cites = {0},
  citedby = {0},
  pages = {369-374},
  booktitle = {8th Asian Test Symposium (ATS  99), 16-18 November 1999, Shanghai, China},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-0315-2},
}