Latency-Guided On-Chip Bus-Network Design

Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak. Latency-Guided On-Chip Bus-Network Design. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(12):2663-2673, 2006. [doi]

Authors

Milenko Drinic

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Darko Kirovski

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Seapahn Megerian

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Miodrag Potkonjak

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