Latency-Guided On-Chip Bus-Network Design

Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak. Latency-Guided On-Chip Bus-Network Design. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(12):2663-2673, 2006. [doi]

Abstract

Abstract is missing.