Johan Lidén Eddeland, Koen Claessen, Nicholas Smallbone, Zahra Ramezani, Sajed Miremadi, Knut Åkesson. Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans. IEEE Trans. on CAD of Integrated Circuits and Systems, 39(12):5247-5260, 2020. [doi]
@article{EddelandCSRMA20,
title = {Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans},
author = {Johan Lidén Eddeland and Koen Claessen and Nicholas Smallbone and Zahra Ramezani and Sajed Miremadi and Knut Åkesson},
year = {2020},
doi = {10.1109/TCAD.2020.2966480},
url = {https://doi.org/10.1109/TCAD.2020.2966480},
researchr = {https://researchr.org/publication/EddelandCSRMA20},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {39},
number = {12},
pages = {5247-5260},
}