Johan Lidén Eddeland, Koen Claessen, Nicholas Smallbone, Zahra Ramezani, Sajed Miremadi, Knut Åkesson. Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans. IEEE Trans. on CAD of Integrated Circuits and Systems, 39(12):5247-5260, 2020. [doi]
Abstract is missing.