The following publications are possibly variants of this publication:
- Automatic generation of hierarchical placement rules for analog integrated circuitsMichael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann. ispd 2010: 47-54 [doi]
- The Sizing Rules Method for Analog Integrated Circuit DesignHelmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich. iccad 2001: 343-349 [doi]
- The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit SynthesisTobias Massier, Helmut E. Graeb, Ulf Schlichtmann. tcad, 27(12):2209-2222, 2008. [doi]
- Routability-driven placement algorithm for analog integrated circuitsCheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang. ispd 2012: 71-78 [doi]
- Hierarchical Characterization of Analog Integrated CMOS CircuitsJosef Eckmueller, Martin Groepl, Helmut E. Graeb. date 1998: 636-643 [doi]