Abstract is missing.
- Lithography till the end of Moore's lawBurn J. Lin. 1-2 [doi]
- Design-aware lithographyShayak Banerjee, Kanak B. Agarwal, Sani R. Nassif. 3-8 [doi]
- Graph-based subfield scheduling for electron-beam photomask fabricationShao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang. 9-16 [doi]
- A polynomial time exact algorithm for self-aligned double patterning layout decompositionZigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong. 17-24 [doi]
- Flexible self-aligned double patterning aware detailed routing with prescribed layout planningJhih-Rong Gao, David Z. Pan. 25-32 [doi]
- 3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applicationsKwang-Ting Tim Cheng, Dmitri B. Strukov. 33-40 [doi]
- A fast estimation of SRAM failure rate using probability collectivesFang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He. 41-48 [doi]
- Integrated fluidic-chip co-design methodology for digital microfluidic biochipsTsung-Wei Huang, Jia-Wen Chang, Tsung-Yi Ho. 49-56 [doi]
- Transformation from ad hoc EDA to algorithmic EDAJason Cong. 57-62 [doi]
- On simulated annealing in EDAMartin D. F. Wong. 63-64 [doi]
- On pioneering nanometer-era routing problemsTong Gao, Prashant Saxena. 65-68 [doi]
- I attended the nineteenth design automation conferenceC. L. Liu. 69-70 [doi]
- Routability-driven placement algorithm for analog integrated circuitsCheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang. 71-78 [doi]
- Keep it straight: teaching placement how to better handle designs with datapathsSamuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan. 79-86 [doi]
- Mixed integer programming models for detailed placementShuai Li, Cheng-Kok Koh. 87-94 [doi]
- Power-grid (PG) analysis challenges for large microprocessor designs: (our experience with oracle sparc processor designs)Alexander Korobkov. 95-96 [doi]
- Efficient on-line module-level wake-up scheduling for high performance multi-module designsMing-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, Shih-Chieh Chang. 97-104 [doi]
- Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graphChung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng. 105-112 [doi]
- TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICsBing Shi, Ankur Srivastava. 113-118 [doi]
- Construction of minimal functional skew clock treesVenky Ramachandran. 119-120 [doi]
- Novel pulsed-latch replacement based on time borrowing and spiral clusteringChih-Long Chang, Iris H.-R. Jiang, Yu-Ming Yang, Evan Y.-W. Tsai, Aki S.-H. Chen. 121-128 [doi]
- On construction low power and robust clock tree via slew budgetingYeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen. 129-136 [doi]
- Optimizing the antenna area and separators in layer assignment of multi-layer global routingWen-Hao Liu, Yih-Lang Li. 137-144 [doi]
- Simultaneous clock and data gate sizing algorithm with common global objectiveGregory Shklover, Ben Emanuel. 145-152 [doi]
- Construction of realistic gate sizing benchmarks with known optimal solutionsAndrew B. Kahng, Seokhyeong Kang. 153-160 [doi]
- The ISPD-2012 discrete cell sizing contest and benchmark suiteMuhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo. 161-164 [doi]
- Towards layout-friendly high-level synthesisJason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabhakar. 165-172 [doi]
- Synthesis for advanced nodes: an industry perspectiveJanet L. Olson. 173-174 [doi]
- Reality-driven physical synthesisPatrick Groeneveld. 175-178 [doi]
- Optimal slack-driven block shaping algorithm in fixed-outline floorplanningJackey Z. Yan, Chris Chu. 179-186 [doi]
- Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chipRenshen Wang, Nimish Shah. 187-192 [doi]
- MAPLE: multilevel adaptive placement for mixed-size designsMyung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji. 193-200 [doi]
- A size scaling approach for mixed-size placementKalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan. 201-206 [doi]